View IC41LV44002AS-50T_5173075.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated circuit solution inc. 1 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) document title 4mx4 bit dynamic ram with edo page mode revision history revision no history draft date remark 0a initial draft september 4,2001 the attached datasheets are provided by icsi. integrated circuit solution inc reserve the right to change the specifications a nd products. icsi will answer to your questions about device. if you have any questions, please contact the icsi offices.
2 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) features ? extended data-out (edo) page mode access cycle ? ttl compatible inputs and outputs ? refresh interval: -- 2,048 cycles/32 ms ? refresh mode: ras -only, cas -before- ras (cbr), and hidden ? jedec standard pinout ? single power supply: 5v 10% or 3.3v 10% ? self refresh 2048 cycles for s version ? low power for l version. description the icsi 44002 series is a 4,194,304 x 4-bit high-performance cmos dynamic random access memory. these devices offer an accelerated cycle access called edo page mode. edo page mode allows 2,048 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. these features make the 44002 series ideally suited for high- bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. the 44002 series is packaged in a 24-pin 300mil soj and a 24 pin tsop-2 4m x 4 (16 - mbit) dynamic ram with edo page mode key timing parameters parameter - 50 - 60 unit ras access time (t rac )5060ns cas access time (t cac )1315ns column address access time (t aa )2530ns edo page mode cycle time (t pc )2025ns read/write cycle time (t rc ) 84 104 ns icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. product series overview part no. refresh voltage is41c44002a 2k 5v 10% is41c44002as(l) 2k 5v 10% is41lv44002a 2k 3.3v 10% is41lv44002as(l) 2k 3.3v 10% 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vcc i/o0 i/o1 we ras nc a10 a0 a1 a2 a3 vcc gnd i/o3 i/o2 cas oe a9 a8 a7 a6 a5 a4 gnd pin descriptions a0-a10 address inputs (2k refresh) i/o0-3 data inputs/outputs we write enable oe output enable ras row address strobe cas column address strobe vcc power gnd ground nc no connection pin configuration 24 pin soj, tsop - 2
integrated circuit solution inc. 3 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) functional block diagram oe we cas cas we oe data i/o bus column decoders sense amplifiers memory array 4,194,304 x 4 row decoder data i/o buffers cas control logic we control logics oe control logic i/o0-i/o3 ras ras a0-a10 ras clock generator refresh counter address buffers truth table function ras ras ras ras ras cas cas cas cas cas we we we we we oe oe oe oe oe address t r /t c i/o standby h h x x x high-z read l l h l row/col d out write: word (early write) l l l x row/col d in read-write l l h ll h row/col d out , d in edo page-mode read 1st cycle: l h l h l row/col d out 2nd cycle: l h l h l na/col d out edo page-mode write 1st cycle: l h l l x row/col d in 2nd cycle: l h l l x na/col d in edo page-mode 1st cycle: l h lh ll h row/col d out , d in read-write 2nd cycle: l h lh ll h na/col d out , d in hidden refresh read l h l l h l row/col d out write (1) l h l l l x row/col d in ras -only refresh l h x x row/na high-z cbr refresh h l l h x x high-z note: 1. early write only.
4 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) functional description the ic41c44002a and ic41lv44002a are cmos drams optimized for high-speed bandwidth, low power applications. during read or write cycles, each bit is uniquely addressed through the 11 address bits. these are entered 11 bits (a0-a10) at a time for the 2k refresh device . the row address is latched by the row address strobe ( ras ). the column address is latched by the column address strobe ( cas ). ras is used to latch the first 11 bits and cas is used to latch the latter 11 bits. memory cycle a memory cycle is initiated by bring ras low and it is terminated by returning both ras and cas high. to ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. a new cycle must not be initiated until the minimum precharge time t rp , t cp has elapsed. read cycle a read cycle is initiated by the falling edge of cas or oe , whichever occurs last, while holding we high. the column address must be held for a minimum time specified by t ar . data out becomes valid only when t rac , t aa , t cac and t oe are all satisfied. as a result, the access time is dependent on the timing relationships between these parameters. write cycle a write cycle is initiated by the falling edge of cas and we , whichever occurs last. the input data must be valid at or before the falling edge of cas or we , whichever occurs last. refresh cycle to retain data, 2,048 refresh cycles are required in each 32 ms period. there are two ways to refresh the memory: 1. by clocking each of the 2,048 row addresses (a0 through a10) with ras at least once every 32 ms. any read, write, read-modify-write or ras -only cycle re- freshes the addressed row. 2. using a cas -before- ras refresh cycle. cas -before- ras refresh is activated by the falling edge of ras , while holding cas low. in cas -before- ras refresh cycle, an internal 11-bit counter provides the row ad- dresses and the external address inputs are ignored. cas -before- ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. self refresh cycle (1) the self refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 64 ms. i. e., 32 s per row when using distributed cbr refreshes. the feature also allows the user the choice of a fully static, low power data retention mode. the optional self refresh feature is initiated by performing a cbr refresh cycle and holding ras low for the specified t rass . the self refresh mode is terminated by driving ras high for a minimum time of t rps . this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras low-to-high transition. if the dram controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram controller utilizes a ras -only or burst refresh sequence, all 2048 rows must be refreshed within the average internal refresh rate, prior to the resump- tion of normal operation. power - on after application of the v cc supply, an initial pause of 200 s is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a ras signal). during power-on, it is recommended that ras track with v cc or be held at a valid v ih to avoid current surges. note: 1.self refresh is for s version only.
integrated circuit solution inc. 5 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) absolute maximum ratings (1) symbol parameters rating unit v t voltage on any pin relative to gnd 5v ? 1.0 to +7.0 v 3.3v ? 0.5 to +4.6 v cc supply voltage 5v ? 1.0 to +7.0 v 3.3v ? 0.5 to +4.6 i out output current 50 ma p d power dissipation 1 w t a commercial operation temperature 0 to +70 o c t stg storage temperature ? 55 to +125 o c note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (voltages are referenced to gnd.) symbol parameter min. typ. max. unit v cc supply voltage 5v 4.5 5.0 5.5 v 3.3v 3.0 3.3 3.6 v ih input high voltage 5v 2.4 ? v cc + 1.0 v 3.3v 2.0 ? v cc + 0.3 v il input low voltage 5v ? 1.0 ? 0.8 v 3.3v ? 0.3 ? 0.8 t a commercial ambient temperature 0 ? 70 o c capacitance (1,2) symbol parameter max. unit c in 1 input capacitance: a0-a10(a11) 5 pf c in 2 input capacitance: ras , cas , we , oe 7pf c io data input/output capacitance: i/o0-i/o3 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 o c, f = 1 mhz.
6 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) electrical characteristics (1) (recommended operating conditions unless otherwise noted.) symbol parameter test condition speed min. max. unit i il input leakage current any input 0v v in vcc ? 55a other inputs not under test = 0v i io output leakage current output is disabled (hi-z) ? 55a 0v v out vcc v oh output high voltage level i oh = ? 5.0 ma with v cc =5v 2.4 ? v i oh = ? 2.0 ma with v cc =3.3v v ol output low voltage level i ol = 4.2 ma with v cc =5v ? 0.4 v i ol = 2 ma with v cc =3.3v i cc 1 standby current: ttl ras , cas v ih 5v ? 2ma 3.3v ? 2 i cc 2 standby current: cmos ras , cas v cc ? 0.2v 5v ? 1ma 3.3v ? 0.5 i cc 3 operating current: ras , cas , -50 ? 120 ma random read/write (2,3,4) address cycling, t rc = t rc (min.) -60 ? 110 average power supply current i cc 4 operating current: ras = v il , cas , -50 ? 90 ma edo page mode (2,3,4) cycling t pc = t pc (min.) -60 ? 80 average power supply current i cc 5 refresh current: ras , cas cycling -50 ? 120 ma cbr (2,3,5) t rc = t rc (min.) -60 ? 110 average power supply current i cc s self refresh current (6) self refresh mode 5v,nromal version 500 a 5v, l version 350 3.3v, normal version 450 3.3, l version 350 notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. dependent on cycle rates. 3. specified values are obtained with minimum cycle time and the output open. 4. column-address is changed once each edo page cycle. 5. enables on-chip refresh and address counters. 6. i ccs is for s version only.
integrated circuit solution inc. 7 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) - 50 - 60 symbol parameter min. max. min. max. units t rc random read or write cycle time 84 ? 104 ? ns t rac access time from ras (6, 7) ? 50 ? 60 ns t cac access time from cas (6, 8, 15) ? 14 ? 15 ns t aa access time from column-address (6) ? 25 ? 30 ns t ras ras pulse width 50 10k 60 10k ns t rp ras precharge time 30 ? 40 ? ns t cas cas pulse width (23) 8 10k 10 10k ns t cp cas precharge time (9) 10 ? 10 ? ns t csh cas hold time (21) 38 ? 40 ? ns t rcd ras to cas delay time (10, 20) 12 37 14 45 ns t asr row-address setup time 0 ? 0 ? ns t rah row-address hold time 8 ? 10 ? ns t asc column-address setup time (20) 0 ? 0 ? ns t cah column-address hold time (20) 8 ? 10 ? ns t rad ras to column-address delay time (11) 10 25 12 30 ns t ral column-address to ras lead time 25 ? 30 ? ns t rsh ras hold time 8 ? 10 ? ns t rhcp ras hold time from cas precharge 30 ? 35 ? ns t clz cas to output in low-z (15, 24) 0 ? 0 ? ns t crp cas to ras precharge time (21) 5 ? 5 ? ns t od output disable time (19, 24) 015 015 ns t oe output enable time (15, 16) ? 12 ? 15 ns t oed output enable data delay (write) 20 ? 20 ? ns t oehc oe high hold time from cas high 5 ? 5 ? ns t oep oe high pulse width 10 ? 10 ? ns t rcs read command setup time (17, 20) 0 ? 0 ? ns t rrh read command hold time 0 ? 0 ? ns (referenced to ras ) (12) t rch read command hold time 0 ? 0 ? ns (referenced to cas ) (12, 17, 21) t wch write command hold time (17) 8 ? 10 ? ns t wp write command pulse width (17) 8 ? 10 ? ns t wpz we pulse widths to disable outputs 10 ? 10 ? ns t rwl write command to ras lead time (17) 13 ? 15 ? ns t cwl write command to cas lead time (17, 21) 8 ? 10 ? ns t wcs write command setup time (14, 17, 20) 0 ? 0 ? ns
8 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) ac characteristics (continued) (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) - 50 - 60 symbol parameter min. max. min. max. units t oeh oe hold time from we during 8 ? 10 ? ns read-modify-write cycle (18) t ds data-in setup time (15, 22) 0 ? 0 ? ns t dh data-in hold time (15, 22) 8 ? 10 ? ns t rwc read-modify-write cycle time 108 ? 133 ? ns t rwd ras to we delay time during 64 ? 77 ? ns read-modify-write cycle (14) t cwd cas to we delay time (14, 20) 26 ? 32 ? ns t awd column-address to we delay time (14) 39 ? 47 ? ns t pc edo page mode read or write 20 ? 25 ? ns cycle time t rasp ras pulse width in edo page mode 50 100k 60 100k ns t cpa access time from cas precharge (15) ? 30 ? 35 ns t prwc edo page mode read-write 56 ? 68 ? ns cycle time t coh data output hold after cas low 5 ? 5 ? ns t off output buffer turn-off delay from 0 12 0 15 ns cas or ras (13,15,19, 24) t whz output disable delay from we 310 310 ns t csr cas setup time (cbr refresh) (20, 25) 5 ? 5 ? ns t chr cas hold time (cbr refresh) ( 21, 25) 8 ? 10 ? ns t rpc ras to cas precharge time 5 ? 5 ? ns t ord oe setup time prior to ras during 0 ? 0 ? ns hidden refresh cycle t ref auto refresh period 2,048 cycles ? 32 ? 32 ms t t transition time (rise or fall) (2, 3) 1501 50ns ac test conditions output load: two ttl loads and 100 pf (vcc=5.0v 10%) one ttl loads and 100 pf (vcc=3.3v 10%) input timing reference levels: v ih = 2.4v, v il = 0.8v output timing reference levels: v oh = 2.0v, v ol = 0.8v
integrated circuit solution inc. 9 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycle ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times, are measured between v ih and v il (or between v il and v ih ) and assume to be 1 ns for all inputs. 3. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. if cas and ras = v ih , data output is high-z. 5. if cas = v il , data output may contain data from the last valid read cycle. 6. measured with a load equivalent to one ttl gate and 50 pf. 7. assumes that t rcd after appli t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 8. assumes that t rcd t rcd (max). 9. if cas is low at the falling edge of ras , data out will be maintained from the previous cycle. to initiate a new cycle and clear the data output buffer, cas and ras must be pulsed for t cp . 10. operation with the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, access time is controlled exclusively by t cac . 11. operation within the t rad (max) limit ensures that t rcd (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t aa . 12. either t rch or t rrh must be satisfied for a read cycle. 13. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 14. t wcs , t rwd , t awd and t cwd are restrictive operating parameters in late write and read-modify-write cycle only. if t wcs t wcs (min), the cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. if t rwd t rwd (min), t awd t awd (min) and t cwd t cwd (min), the cycle is a read-write cycle and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write ( oe -controlled) cycle. 15. output parameter (i/o) is referenced to corresponding cas input. 16. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open. if oe is tied permanently low, a late write or read-modify-write is not possible. 17. write command is defined as we going low. 18. late write and read-modify-write cycles must have both t od and t oeh met ( oe high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the i/os will provide the previously written data if cas remains low and oe is taken back to low after t oeh is met. 19. the i/os are in open during read cycles once t od or t off occur. 20. determined by falling edge of cas . 21. determined by rising edge of cas . 22. these parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read- modify-write cycles. 23. cas must meet minimum pulse width. 24. the 3 ns minimum is a parameter guaranteed by design. 25. enables on-chip refresh and address counters.
10 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) read cycle note: 1. t off is referenced from rising edge of ras or cas , whichever occurs last. t ras t rc t rp t cah t asc t rad t ral oe i/o we address cas ras row column row open open valid data t csh t cas t rsh t crp t rcd t rah t asr t rrh t rch t rcs t aa t cac t off (1) t rac t clz t oe t od
integrated circuit solution inc. 11 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) early write cycle ( oe = don't care) t ras t rc t rp t cah t asc t rad t ral i/o we address cas ras row column row t csh t cas t rsh t crp t rcd t rah t asr t cwl t wch t rwl t wp t wcs t dh t ds valid data
12 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) read write cycle (late write and read-modify-write cycles) t ras t rwc t rp t cah t asc t rad t ral we oe address cas ras row column row t csh t cas t rsh t crp t rcd t rah t asr t rwd t cwl t cwd t rwl t awd t wp t rcs t cac t clz t ds t dh t oeh t od t oe t rac t aa i/o open open valid d out valid d in
integrated circuit solution inc. 13 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) edo - page - mode read cycle note: 1. t pc can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas . both measurements must meet the t pc specifications. t rasp t rp address cas ras row row t cas t crp t rcd t csh t cp t cas t cah t cas t ral t rsh t cp t cp t pc (1) t asr t rah t rad column column t cah t cah column t asc t asc oe i/o we open open valid data t aa t aa t cpa t cac t cac t rac t coh t clz t oep t oe t od t oe t oehc valid data t rch t rrh t aa t cpa t cac t off t clz valid data t od t asc t rcs
14 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) edo - page - mode early - write cycle t rasp t rp address cas ras row row t cas t crp t rcd t csh t cp t cas t cah t cas t ral t rsh t cp t cp t pc t asr t rah t rad column column t cah t cah column t asc t asc oe i/o we valid data t asc t wcs t wch t cwl t wp t wcs t wch t cwl t wp t ds t dh t wcs t wch t cwl t wp valid data t ds t dh valid data t ds t rwl t dh
integrated circuit solution inc. 15 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) edo - page - mode read - write cycle (late write and read-modify write cycles) note: 1. t pc is for late write only. t pc can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas . both measurements must meet the t pc specifications. t rasp t rp address cas ras row row t crp t rcd t csh t cp t cah t cas t ral t rsh t cp t cp t rah t rad t asr column column t cah t cah column t asc t asc t cas t cas oe i/o we t asc t rwd t rcs t cwl t wp t awd t cwd t dh t ds t cac t clz t awd t cwd t cwl t wp t awd t cwd t cwl t rwl t wp open open d in d out t oe t oe t oe t od t oeh t od t od t dh t ds t cpa t aa t cac t clz d in d out t dh t ds t cac t clz d in d out t cpa t aa t rac t aa t pc / t prwc (1)
16 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) edo - page - mode read - early - write cycle (psuedo read-modify write) t rasp t rp address cas ras row row t crp t rcd t pc t csh t cp t cah t cas t ral t rsh t cp t cp t rah t rad t asr column (a) column (n) t cah t cah column (b) t asc t asc t cas t cas oe i/o we t asc t cac t rch t dh open open valid data (a) t oe t wcs t cac t coh d in t cpa t wch t rac t aa t pc valid data (b) t whz t ds t rcs t aa
integrated circuit solution inc. 17 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) ac waveforms read cycle (with we -controlled disable) ras ras ras ras ras - only refresh cycle ( oe , we = don't care) t cah t asc t asc t rad oe i/o we address cas ras row column open open valid data t csh t cas t crp t rcd t cp t rah t asr t rch t rcs t rcs t aa t cac t whz t rac t clz t clz t oe t od column t ras t rc t rp i/o address cas ras row row open t crp t rah t asr t rpc
18 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) hidden refresh cycle (1) ( we = high; oe = low) cbr refresh cycle (addresses; oe = don't care, we =high) notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high. 2. t off is referenced from rising edge of ras or cas , whichever occurs last. t ras t ras t rp t rp i/o cas ras open t cp t rpc t csr t chr t rpc t csr t chr t ras t ras t rp cas ras t crp t rcd t rsh t chr t asc t rad address row column t rah t asr t ral t cah i/o open open valid data t aa t cac t rac t clz t off (2) oe t oe t ord t od
integrated circuit solution inc. 19 dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) self refresh cycle (addresses : we and oe = don't care) t rass t rp t rps dq cas ras open t cp v ih v il v ih v il v oh v ol t rpc t csr t chd t rpc t cp timing parameters -50 -60 symbol min. max. min. max. units t chd 10 ? 10 ? ns t cp 9? 9? ns t csr 10 ? 10 ? ns t rass 100 ? 100 ? s t rp 30 ? 40 ? ns t rps 84 ? 104 ? ns t rpc 5? 5? ns
20 integrated circuit solution inc. dr026-0a 09/04/2001 ic41c44002a/ic41c44002as(l) ic41lv44002a/ic41lv44002as(l) integrated circuit solution inc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw ordering information commercial range: 0 c to 70 c voltage: 5v speed (ns) order part no. refresh package 50 ic41c44002a-50j 2k 300mil soj 50 ic41c44002a-50t 2k 300mil tsop-2 60 ic41c44002a-60j 2k 300-mil soj 60 ic41c44002a-60t 2k 300mil tsop-2 speed (ns) order part no. refresh package 50 ic41c44002as-50j 2k 300mil soj 50 ic41c44002as-50t 2k 300mil tsop-2 50 ic41c44002asl-50j 2k 300mil soj 50 ic41c44002asl-50t 2k 300mil tsop-2 60 ic41c44002as-60j 2k 300mil soj 60 ic41c44002as-60t 2k 300mil tsop-2 60 ic41c44002asl-60j 2k 300mil soj 60 ic41c44002asl-60t 2k 300mil tsop-2 voltage: 3.3v speed (ns) order part no. refresh package 50 ic41lv44002a-50j 2k 300mil soj 50 ic41lv44002a-50t 2k 300mil tsop-2 60 ic41lv44002a-60j 2k 300mil soj 60 ic41lv44002a-60t 2k 300mil tsop-2 speed (ns) order part no. refresh package 50 ic41lv44002as-50j 2k 300mil soj 50 IC41LV44002AS-50T 2k 300mil tsop-2 50 ic41lv44002asl-50j 2k 300mil soj 50 ic41lv44002asl-50t 2k 300mil tsop-2 60 ic41lv44002as-60j 2k 300mil soj 60 ic41lv44002as-60t 2k 300mil tsop-2 60 ic41lv44002asl-60j 2k 300mil soj 60 ic41lv44002asl-60t 2k 300mil tsop-2

▲Up To Search▲

Price & Availability of IC41LV44002AS-50T

	To Download IC41LV44002AS-50T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .